#8 bit parallel in serial out shift register vhdl code code#

If you check the code above then you can see that the code is written using some if.else.

If ( Load =' 0' ) then -Do the serial right shifting here.Д®lse -Load the registers with a new value to shift. Signal Load_value : std_logic_vector ( 3 downto 0 ) := '0000' Parallel_In : IN std_logic_vector ( 3 downto 0 ) 2 (Error because freq of pulse is less than system clock) Uut : entity work.pulse_counter PORT MAP ( The testbench code used for testing the design is given below: Prev_Count <= Curr_Count -Re-setting the Prev_Count. Increment Curr_Count every clock cycle.This is the max freq which can be measured by the module.Д®RR_O <= ' 1' -Error bit is inserted here. Signal Curr_Count,Prev_Count : unsigned ( 47 downto 0 ) := ( others => ' 0' ) Port ( DAT_O : out unsigned ( 47 downto 0 ) Д®RR_O : out std_logic -This is '1' if the pulse freq is more than clk freq.ДЄrchitecture Behavioral of pulse_counter is

#8 bit parallel in serial out shift register vhdl code update#

Otherwise the module will output the time period as '0' and a '1' will be asserted in the ERR_O output.ДҐ)Whenever we calculate the time period of the pulse we update the prev_count with the current value of count.Д¦)Note that at time 1460.004 ns, at the new positive edge of pulse cycle we have a new time period calculated which is 130000 in relative terms or 1300 ns in absolute scale. Here we multiply 15000 with 10 ps = 150 ns.Д¤) For all this to work with good precision the frequency of the system clock should be very high compared to the frequency of pulse input. For getting the exact time period is ns you have to multiply the time period of system clock with the calculated value. This is how we get 15000 as the time period of the pulse input in terms of system clock.

But all this time curr_count keeps on counting with the system clock.ДЈ) pulse goes to '1' at 160 ns. Prev_Count is made '1000' which is the curr_count at 10 ns.Дў) pulse goes to '0' at 110 ns. In the second part we simply subtracts the last count from the current count to get the time period of the pulse in terms of the time period of the system clock.ДЇor example if you see the simulation waveform I have attached at the bottom of this page you can see how this works:ДЎ) pulse goes to '1' at 10 ns.

#8 bit parallel in serial out shift register vhdl code how to#

This article is about how to find the time period of an input pulse using a simple counter and some adders.In some applications you may have a pulse input which has unknown or varying frequency.And you may need to find out this frequency.In this design I have two parts.ДЇirst part is a counter which keeps on incrementing at the system clock frequency.When this counter reaches its maximum value it resets automatically and counts up again.The second part is triggered at every positive edge of the pulse input.So this part is triggered once every clock cycle of the pulse. So as you can see from the examples using 'generate' keyword makes your design simple to understand and saves your time. Signal D,Q : unsigned ( 3 downto 0 ) := '0000' ДЇ1 : if ( i / = 0 ) generate -generating the rest of the three FF's.Д«egin U2 : entity work.example_FDRSE port map -usual port mapping Two AND gates with a OR gate is used for this.Д ( 1 ) <= (Load_value ( 2 ) and Load ) or (Q ( 0 ) and not (Load ) ) Д ( 2 ) <= (Load_value ( 1 ) and Load ) or (Q ( 1 ) and not (Load ) ) Д ( 3 ) <= (Load_value ( 0 ) and Load ) or (Q ( 2 ) and not (Load ) ) ДЄrchitecture Behavioral of johnson_counter is

The D inputs of the flip flops are controlled with the load input. Signal D,Q,Load_value : std_logic_vector ( 3 downto 0 ) := '0000' Load=1 means register is loaded parallely and Load=0 means right shift by one bit. Parallel_In : in std_logic_vector ( 3 downto 0 ) 4 bit Parallel In Serial Out shift register(LSB is out first)